Traditionally, clock and data recovery (CDR) has been utilized for extracting a clock from received data which is often distorted by transport media, and using such clock to re-time the data from the received data. Oftentimes, CDR is used in chip-to-chip interface applications. However, traditional implementations of clock data recovery have generally exhibited various limitations.
For example, CDR uses phase detection for detecting a phase (e.g. phase error) associated with the received data. Unfortunately, performing such phase lock has conventionally been limited to use of a fixed charge pump current setting associated with a passive or digital loop filter in the CDR, such that the phase is adjusted utilizing a constant charge pump current together until a phase lock of the data is performed. As a result, when tracking high frequency sinusoidal jitter, the CDR employing the fixed charge pump current control setting experiences a slew-rate limited tracking process and the jitter tolerance performance is degraded due to a limited equivalent bandwidth. Similar problems do not only exist with respect to charge pump based CDR or phase-locked loop (PLL), but also exist with respect to phase interpolator based CDR which pick or adjusts its phase from many interpolated clock phases.
There is thus a need for addressing these and/or other issues associated with the prior art.